Helen graduated from the University of Tianjin in 2000 with a double major in CS and Economics. In 2007, she embarked on her career with NEC in Japan as an IP/SoC engineer focusing on both design and verification. Shortly after, she joined Cadence in October of 2007 and worked in the Global Service Group. In 2012, she transferred to the Intellectual Property Group focusing her career on Cadence’s DDR design which stands for ‘Double Data Rate’. Her team focuses on the design of high speed memory IP like DDRx (DDR3/4/5), LPDDRx (LPDDR3/4/4X/5) and HBM (High Bandwidth Memory) which is broadly used in both enterprise/server and consumer SoC products. Her passion for debugging failures and finding the root cause of issues, has allowed Helen to grow her career at Cadence.