Dr. Tahrina Ahmed is Senior Director of Design Enablement Group, Tensilica IP Group at Cadence Tensilica IP Group. Before joining Cadence Design Systems, she was Principal CPU Architect and Sr. Engineering Manager at Advanced Micro Devices leading the team responsible for defining AMD client architecture and roadmap decisions. Previously she was at Intel Corporation as Lead Performance Architect and Engineering Manager responsible for Client, Server and Cloud segments. Tahrina graduated from Stanford University with a PhD in Electrical Engineering, where her research focused on Distributed Domain Specific Architecture. In her limited spare time, she enjoys reading, hiking, classical dancing and spending time with her family.